This application is related to Korean Application No. 2001-05147, filed Feb. 2, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit memory devices and methods of fabricating the same and, more particularly, to integrated circuit ferroelectric memory devices and methods of fabricating the same.
Integrated circuit memory devices can be classified into two categories, volatile memory devices and non-volatile memory devices. Non-volatile memory devices, for example, flash memory, magnetic tape and/or magnetic floppy disks, can maintain stored data when the power supply to the memory device is blocked.
In contrast, volatile memory devices may lose stored data when the power supply to the memory device is blocked. Volatile memory devices may include, for example, static random access memory (SRAM) and/or dynamic random access memory (DRAM). Although DRAM devices may be highly integrated using a transistor and capacitor memory cell arrangement, these devices may require a periodic refresh operation in order to maintain stored data when the power supply to the memory device is blocked.
It may be possible to use a capacitor memory cell of a DRAM structure when a ferroelectric material is formed between two electrodes of the capacitor, such as in, for example, a ferroelectric random access memory (FRAM) device. FRAM devices may exhibit characteristics of non-volatile memory devices due to the ferroelectric material between a pair of capacitor electrodes. Thus, a FRAM device has two different stable polarization states. The two polarization states are typically inverted according to the direction of the applied voltage and the inverted polarization states are typically maintained when the applied voltage is blocked.
A FRAM device may be non-volatile. FRAM devices are typically programmable with a low voltage, for example, less than about 5V, have less than about a 40 nanosecond access time, and have a robustness with respect to virtually unlimited numbers of read/write cycles, for example, more than about 1xc3x971012 cycles. Flash memory devices are typically programmable with voltages from about 18V to about 22V, have access times of about a couple of microseconds, and a robustness with respect to from about 1xc3x97105 to about 1xc3x97106 cycles. FRAM devices also typically do not consume a lot of power and exhibit radiation hardness.
Now referring to FIGS. 1 and 2, typical equivalent circuits of ferroelectric memory devices will be discussed. As shown in FIG. 1, a two transistor/two capacitor (2T/2C) ferroelectric memory device 10 includes a first transistor T1 coupled to a first ferroelectric capacitor CF1 and a second transistor T2 coupled to a second ferroelectric capacitor CF2. The first and second ferroelectric capacitors CF1 and CF2 store complementary polarization states. The complementary polarization states define a single data state. A plate line PL is coupled to one side of the first and second ferroelectric capacitors CF1 and CF2 and runs parallel to a word line WL that is coupled to the gates of the first and second transistors T1 and T2. A pair of complementary bit lines BL and BLxe2x80x2 are coupled to one side of the first and second transistors T1 and T2.
As illustrated in FIG. 2, a one transistor/one capacitor (1T/1C) ferroelectric memory device 20 includes one transistor T and one ferroelectric capacitor CF coupled to one terminal (one of a source region and a drain region) of the transistor T. One word line WL is coupled to a gate of the transistor T and one bit line BL is coupled to the other terminal (the other of the source region and the drain region) of the transistor T and a respective plate line PL is coupled to a second electrode of the ferroelectric capacitor CF.
In the equivalent circuits of FIGS. 1 and 2, an electrical pulse may be applied to a second electrode of the ferroelectric capacitor to trigger a data read/write operation. To enable the data read/write operation, a plate line is formed such that it is electrically connected to the second electrode through a contact hole as described with respect to FIG. 3.
Now referring to FIG. 3, methods of fabricating conventional ferroelectric memory devices will be described. A contact plug 302 is formed in a contact hole in a first insulating layer 300. The contact plug 302 is electrically connected to one of the source region and/or the drain region of a transistor in an underlying substrate. A ferroelectric capacitor CF is formed on the first insulating layer 300 and is electrically connected to the contact plug 302. The ferroelectric capacitor CF typically includes a first electrode 304, a ferroelectric film 306 and a second electrode 308. A second insulating layer 310 is typically formed on the ferroelectric capacitor CF and on the first insulating layer 300. A plate line 314 is formed on the second insulating layer 310 and is electrically connected to the second electrode 308. The plate line 314 is formed by the steps of patterning the second insulating layer 310 to form a contact hole 312 that exposes the second electrode 308, depositing a plate line conductive material on the second insulating layer 310 and in the contact hole 312, and patterning the deposited conductive material to form the plate line 314.
As integrated circuit memory devices decrease in size, the contact holes may also become smaller and the insulating layer over the ferroelectric capacitor may become thicker. As a result, a photo-etching process used to interconnect the second electrode and the plate line may become more difficult to perform accurately. For example, when a small contact hole is formed in a thick insulating layer, the contact hole may be incompletely opened and/or a reliable contact resistance between the plate line and the second electrode may not be secured. Furthermore, if a stripe line is formed to improve a conductivity of the word line, an electrical bridge between the stripe line and the plate line may occur if the contact hole is misaligned.
Embodiments of the present invention provide integrated circuit ferroelectric memory devices including integrated circuit transistors. The memory device further includes a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween. The memory device still further includes a plate line directly on the ferroelectric capacitor.
In some embodiments of the present invention the plate line may be directly on the second electrode of the ferroelectric capacitor. The integrated circuit ferroelectric memory device may be free of a plug between the plate line and the second electrode. The integrated circuit ferroelectric memory device may further be free of an insulating layer between the plate line and the second electrode. Furthermore, the second electrode may have a width and the plate line may be directly on the second electrode across the width.
In further embodiments of the present invention a stripe line may be provided adjacent the second electrode and remote from the first electrode. Alternatively, a stripe line may be provided between the second electrode and the transistor. The stripe line may include aluminum.
In still further embodiments of the present invention the first electrode may include at least one of platinum and/or iridium dioxide. The ferroelectric film may include at least one of PZT, SBT and/or BLT. The second electrode may include at least one of iridium, ruthenium, platinum and/or iridium dioxide.
Some embodiments of the present invention include methods of fabricating integrated circuit ferroelectric memory devices, including forming an integrated circuit transistor. These embodiments further include forming a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferrolectric film therebetween. These embodiments still further include forming a plate line directly on the ferroelectric capacitor.
In further embodiments of the present invention forming the ferroelectric capacitor may include forming a first electrode layer on the transistor, forming a ferroelectric layer on the first electrode layer, forming a second electrode layer on the ferroelectric layer, and etching the first electrode layer, the ferroelectric layer and the second electrode layer to form the first electrode, the ferroelectric film and the second electrode, respectively.
In still further embodiments of the present invention forming the plate line may include forming an insulating layer on the ferroelectric capacitor, planarizing the insulating layer to expose at least a portion of the second electrode, forming a plate line conductive layer on the second electrode and the insulating layer and etching the plate line conductive layer to form the plate line directly on the second electrode of the ferroelectric capacitor.